The demand for increased functionality and high-speeds in circuits such as direct digital synthesizers (DDS) necessitates faster memory circuit architectures, such as read only memory (ROM). For instance, heterojunction bipolar transistor (HBT) based ROMs commonly cascade an array of logic gates in front of a buffer-based address decoder and after the sense amplifier array of the word decoder to effect a compression ratio for the ROM. In general, compression enables among other things increased speed and decreased die size. However, there are a number of issues associated with such conventional ROM architectures. For instance, the addition of such logic stages significantly reduces the maximum speed of the ROM. In addition, the added circuitry increases the overall size and power usage of the circuit.